Physical Verification Sign-off Engineer

MediaTek

Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
Co-work with Place & Route team to resolve full-chip layout integration issues.
Coordinates with internal IP owners on IP related issues.
Coordinates with Manufacturing Team on DRC related issues.
Provide automation solutions to improve efficiency in tape-out flow.
Report on tapeout issues

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